NDMA - Revision history

Neimod at 07:44, 26 November 2010

2010-11-26T06:44:19Z

← Older revision		Revision as of 09:44, 26 November 2010
Line 244:		Line 244:

	== No immediate and no repeating mode ==		== No immediate and no repeating mode ==
	Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled ~~until~~ the total number of words in REG_NDMATCNT are transferred.		Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled when the total number of words in REG_NDMATCNT are transferred.

Neimod at 07:43, 26 November 2010

2010-11-26T06:43:52Z

← Older revision		Revision as of 09:43, 26 November 2010
Line 241:		Line 241:

	== Repeating mode ==		== Repeating mode ==
	Transfers the words specified in ~~REG_NDMACNT~~ following the startup mode event. REG_DMATCNT is ignored.		Transfers the words specified in REG_NDMAWCNT following the startup mode event. REG_DMATCNT is ignored.

	== No immediate and no repeating mode ==		== No immediate and no repeating mode ==
	Transfers the total number of words in REG_NDMATCNT.		Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled until the total number of words in REG_NDMATCNT are transferred.

Yellows8 at 23:15, 25 November 2010

2010-11-25T22:15:45Z

← Older revision		Revision as of 01:15, 26 November 2010
Line 150:		Line 150:
	== Startup modes (27-24) for ARM9 ==		== Startup modes (27-24) for ARM9 ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! ~~BIT~~		! VALUE
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
Line 191:		Line 191:
	== Startup modes (27-24) for ARM7 ==		== Startup modes (27-24) for ARM7 ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! ~~BIT~~		! VALUE
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-

Neimod at 06:24, 25 November 2010

2010-11-25T05:24:42Z

@@ Line 186: / Line 186: @@
 |  Camera
 |}
 == Block transfers ==

Neimod at 04:56, 25 November 2010

2010-11-25T03:56:52Z

@@ Line 123: / Line 123: @@
 |-
 |  14-13
-|  Source address update method. 0=Increment, 1=Decrement, 2=Fixed, 3=No address(?)
+|  Source address update method. 0=Increment, 1=Decrement, 2=Fixed, 3=No address (for filling)
 |-
 |  15
@@ Line 186: / Line 186: @@
 |  Camera
 |}

Neimod at 04:36, 25 November 2010

2010-11-25T03:36:42Z

← Older revision		Revision as of 06:36, 25 November 2010
Line 117:		Line 117:
	\|-		\|-
	\| 11-10		\| 11-10
	\| Destination address update method.		\| Destination address update method. 0=Increment, 1=Decrement, 2=Fixed.
	\|-		\|-
	\| 12		\| 12
Line 123:		Line 123:
	\|-		\|-
	\| 14-13		\| 14-13
	\| Source address update method.		\| Source address update method. 0=Increment, 1=Decrement, 2=Fixed, 3=No address(?)
	\|-		\|-
	\| 15		\| 15
Line 148:		Line 148:


	== Startup modes (27-24) ==		== Startup modes (27-24) for ARM9 ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT

Neimod at 04:31, 25 November 2010

2010-11-25T03:31:37Z

@@ Line 129: / Line 129: @@
 |-
 |  19-16
-|  Block transfer word count.
+|  Block transfer word count = (1<<x) words.
 |-
 |  27-24
@@ Line 145: / Line 145: @@
 |  31
 |  Enable/busy flag.
 |}

Neimod at 04:26, 25 November 2010

2010-11-25T03:26:58Z

← Older revision		Revision as of 06:26, 25 November 2010
Line 60:		Line 60:
	\| Source data address. Must be multiple of 4.		\| Source data address. Must be multiple of 4.
	\|}		\|}
	Like old DMA, ~~REG_NDMA_SRC~~ is copied to internal registers when written to.		Like old DMA, REG_NDMASAD is copied to internal registers when written to.

	== REG_NDMADAD ==		== REG_NDMADAD ==
Line 87:		Line 87:
	\|-		\|-
	\| 23-0		\| 23-0
	\| ~~Total number~~ of words to transfer.		\| Number of words to transfer.
	\|}		\|}

Neimod at 04:23, 25 November 2010

2010-11-25T03:23:46Z

← Older revision		Revision as of 06:23, 25 November 2010
Line 70:		Line 70:
	\| Destination data address. Must be multiple of 4.		\| Destination data address. Must be multiple of 4.
	\|}		\|}
	Like old DMA, ~~REG_NDMA_DEST~~ is copied to internal registers when written to.		Like old DMA, REG_NDMADAD is copied to internal registers when written to.

	== REG_NDMATCNT ==		== REG_NDMATCNT ==
Line 77:		Line 77:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 31-0		\| 27-0
	\| ~~Number~~ of ~~bytes to copy/write, see REG_NDMA_CNT bit28~~.		\| Total number of words transferred.
	\|}		\|}

Line 86:		Line 86:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 31-0		\| 23-0
	\| ~~Number~~ of ~~bytes~~ to ~~copy/write, see REG_NDMA_CNT bit28~~.		\| Total number of words to transfer.
	\|}		\|}

Line 95:		Line 95:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 31-0		\| 15-0
	\| ~~Time related?~~		\| Interval timer.
			\|-
			\| 17-16
			\| Prescaler. 0=System freq, 1=1/4th freq, 2=1/16th freq, 3=1/64th freq.
	\|}		\|}

Line 105:		Line 108:
	\|-		\|-
	\| 31-0		\| 31-0
	\| ~~Value to write to destination instead of copying when REG_NDMA_CNT bit13 and bit14 are set~~.		\| Fill data.
	\|}		\|}

Line 113:		Line 116:
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| 10-0		\| 11-10
	\| ?		\| Destination address update method.
	\|-		\|-
	\| 11		\| 12
	\| ~~Fixed destination~~ address ~~when set~~.		\| Destination address reload flag.
	\|-		\|-
	\| 12		\| 14-13
	\| ?		\| Source address update method.
	\|-		\|-
	\| 13		\| 15
	\| ~~When set clear data with the value REG_NDMA_CLEAR instead of copying~~.		\| Source address reload flag.
	\|-		\|-
	\| 14		\| 19-16
	\| ~~Fixed source address when set~~.		\| Block transfer word count.
	\|-		\|-
	\| 27-15		\| 27-24
	\| ?		\| Startup mode.
	\|-		\|-
	\| 28		\| 28
	\| ~~Set when REG_NDMA_NUM0 was set, clear when REG_NDMA_NUM1 was set~~.		\| Immediate mode.
			\|-
			\| 29
			\| Repeating mode.
	\|-		\|-
	\| 30		\| 30
Line 138:		Line 144:
	\|-		\|-
	\| 31		\| 31
	\| Enable/busy		\| Enable/busy flag.
	\|}		\|}

Neimod at 04:17, 25 November 2010

2010-11-25T03:17:53Z

← Older revision		Revision as of 06:17, 25 November 2010
Line 7:		Line 7:
	! WIDTH		! WIDTH
	\|-		\|-
	\| ~~REG_NDMA_MASTER_CNT~~		\| REG_NDMAGCNT
	\| 0x04004100		\| 0x04004100
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_SRC~~(n)		\| REG_NDMASAD(n)
	\| 0x04004104 + (n*0x1c)		\| 0x04004104 + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_DEST~~(n)		\| REG_NDMADAD(n)
	\| 0x04004108 + (n*0x1c)		\| 0x04004108 + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_NUM0~~(n)		\| REG_NDMATCNT(n)
	\| 0x0400410c + (n*0x1c)		\| 0x0400410c + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_NUM1~~(n)		\| REG_NDMAWCNT(n)
	\| 0x04004110 + (n*0x1c)		\| 0x04004110 + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_14~~(n)		\| REG_NDMABCNT(n)
	\| 0x04004114 + (n*0x1c)		\| 0x04004114 + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_CLEAR~~(n)		\| REG_NDMAFDATA(n)
	\| 0x04004118 + (n*0x1c)		\| 0x04004118 + (n*0x1c)
	\| 4		\| 4
	\|-		\|-
	\| ~~REG_NDMA_CNT~~(n)		\| REG_NDMACNT(n)
	\| 0x0400411c + (n*0x1c)		\| 0x0400411c + (n*0x1c)
	\| 4		\| 4
	\|}		\|}

	== ~~REG_NDMA_MASTER_CNT~~ ==		== REG_NDMAGCNT ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
	! DESCRIPTION		! DESCRIPTION
	\|-		\|-
	\| ~~15-0~~		\| 19-16
	~~\| ?~~		\| Cycle selection.
	\|-
	\| 16
	\| ~~Unknown, set when initialized by Arm7?~~
	\|-
	~~\| 17~~
	~~\| Unknown, set when initialized by Arm9?~~
	\|-
	~~\| 18~~
	~~\| Unknown, set when initialized by Arm7/Arm9?~~
	\|-
	~~\| 30-19~~
	~~\| ?~~
	\|-		\|-
	\| 31		\| 31
	\| ~~Might be master NDMA enable~~, ~~when initialized this is set?~~		\| DMA arbitration method. 0=Fixed method, 1=Round robin
	\|}		\|}

	== ~~REG_NDMA_SRC~~ ==		== REG_NDMASAD ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 70:		Line 58:
	\|-		\|-
	\| 31-0		\| 31-0
	\| Source data address.		\| Source data address. Must be multiple of 4.
	\|}		\|}
	Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.		Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.

	== ~~REG_NDMA_DEST~~ ==		== REG_NDMADAD ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 80:		Line 68:
	\|-		\|-
	\| 31-0		\| 31-0
	\| Destination data address.		\| Destination data address. Must be multiple of 4.
	\|}		\|}
	Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.		Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.

	== ~~REG_NDMA_NUM0~~ ==		== REG_NDMATCNT ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 93:		Line 81:
	\|}		\|}

	== ~~REG_NDMA_NUM1~~ ==		== REG_NDMAWCNT ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 102:		Line 90:
	\|}		\|}

	== ~~REG_NDMA_14~~ ==		== REG_NDMABCNT ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 111:		Line 99:
	\|}		\|}

	~~Once the CNT bit31 enable bit is set, starting doing the DMA once the time units specified by this register elapses?~~		== REG_NDMAFDATA ==

	== ~~REG_NDMA_CLEAR~~ ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT
Line 122:		Line 108:
	\|}		\|}

	== ~~REG_NDMA_CNT~~ ==		== REG_NDMACNT ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! BIT		! BIT